Auteur / Autrice : | Yangyang Tang |
Direction : | Emmanuel Boutillon, Christophe Jego, Michel Jézéquel |
Type : | Thèse de doctorat |
Discipline(s) : | STIC |
Date : | Soutenance en 2013 |
Etablissement(s) : | Lorient |
Ecole(s) doctorale(s) : | École doctorale Santé, information-communication et mathématiques, matière (Brest, Finistère) |
Partenaire(s) de recherche : | autre partenaire : Université européenne de Bretagne (2007-2016) |
Mots clés
Mots clés contrôlés
Résumé
Although materials could be fabricated as error-free theoretically with a huge cost for worst-case design methodologies, the circuit is still susceptible to transient faults by the effects of radiation, temperature sensitivity, and etc. On the contrary, an error-resilient design enables the manufacturing process to be relieved from the variability issue so as to save material cost. Since variability and transient upsets are worsening as emerging fabrication process and size shrink are tending intense, the requirement of robust design is imminent. This thesis addresses the issue of designing on unreliable circuit. The main contributions are fourfold. Firstly a fast error-correction and low cost redundancy fault-tolerant method is presented. Moreover, we introduce judicious two-dimensional criteria to estimate the reliability and the hardware efficiency of a circuit. A general-purpose model offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures. At last, a decoder against internal transient faults is designed in this work.