Modélisation et conception de circuits intégrés tridimensionnels

Modeling and design of 3D Imager IC

• Auteur / Autrice : Vijayaragavan Viswanathan
• Direction : Ian O'Connor, David Navarro
• Type : Thèse de doctorat
• Discipline(s) : Electronique
• Date : Soutenance le 06/09/2012
• Etablissement(s) : Ecully, Ecole centrale de Lyon
• Ecole(s) doctorale(s) : École doctorale Électronique, électrotechnique, automatique (Lyon)
• Partenaire(s) de recherche : Laboratoire : INL - Institut des Nanotechnologies de Lyon, UMR5270 (Rhône)
• Jury : Président / Présidente : Luc Hebrard
• Jury : Examinateurs / Examinatrices : Olivier Le Briz, Lioua Labrak
• Jury : Rapporteur / Rapporteuse : Yusuf Leblebici, Patrick Garda

Mots clés

Mots clés contrôlés

Circuits intégrés

Imagerie tridimensionnelle

MOS complémentaires

Mots clés libres

CMOS

Intégration tridimensionnelle

Fronts de Pareto

CMOS image sensor

3D imager IC

Pareto front methodology

Résumé

Pas de résumé

CMOS image sensor based on Active pixel sensor has considerably contributed to the imaging market and research interest in the past decade. Furthermore technology advancement has provided the capability to integrate more and more functionality into a single chip in multiple layers leading to a new paradigm, 3D integration. CMOS image sensor is one such application which could utilize the capability of 3D stacked architecture to achieve dedicated technologies in different layers, wire length reduction, less area, improved performancesThis research work is focused mainly on the early stages of design space exploration using hierarchical approach and aims at reducing time to market. This work investigates the imager from the top-down design perspective. Methodical anal y sis of imager is performed to achieve high level of flexibility and modularity. Re-useable models are developed to explore early design choices throughout the hierarchy. Finally, pareto front (providing trade off solutions) methodology is applied to explore the operating range of individual block at system level to help the designer making his design choice. Furthermore the thermal issues which get aggravated in the 3D stacked chip on the performance of the imager are studied. Systeme based thermal model is built to investigate the behavior of imager pixel matrix and to simulate the pixel matrix at high speed with acceptable accuracy compared to electrical simulations. The modular nature of the model makes simulations with future matrix extension straightforward. Validation of the thermal model with respect to electrical simulations is discussed. Finally an integrated design flow is developed to perform 3D floorplanning and to perform thermal anal y sis of the imager pixel matrix.