Projet de thèse en Informatique
Sous la direction de Frédéric Petrot (mstii).
Thèses en préparation à l'Université Grenoble Alpes (ComUE) , dans le cadre de Mathématiques, Sciences et technologies de l'information, Informatique , en partenariat avec TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des Ordinateurs (laboratoire) depuis le 01-10-2013 .
Pas de résumé en français disponible.
Optimize method for cache location in NOC-based Systems
Today thanks to the new deep submicron technologies as well as the 3D-Integration technologies we can easily imagine that the integration of billions and billions of transistors in a single chip as a System-on-Chip (SoC) is becoming real. However with such a huge number of transistors, due to the power consumption and physical limits, instead of constructing a single large complex processor and the use of a high clock frequency, the trend is to use several simple low-power low-frequency processor elements in parallel. International Technology Roadmap for Semiconductor (ITRS) predicts that in 2025 a SoC will contain more than 4500 processing cores. In such Massively-Parallel Multi-Processor SoCs (MP²-SoCs) the memory should also consist of different separate blocks physically distributed over the system in which the memory space is shared between processing elements. Moreover in a shared-memory MP-SoC not only the memory space is shared but also the caches should be shared between processors and memories if there is more than one level of cache. The problem for this kind of architecture is to find the best place for shared caches. As the latency of communications with cashes is critical, finding the optimal location for caches which are shared between several processors and memories located in different places is not evident and is a challenging issue. Furthermore in order to keep cache coherency and cache transparency (i.e. hidden from the processor and memory point of view) the communication infrastructure (e.g. Network-on-Chip : NoC) must support some particular cost-efficient features to route the packet from a processor to the corresponding cache which is hidden from the view of the processor, from a cache to the proper memory, and the corresponding responses from memories to caches and from caches to processors. The current PhD proposition is to address these types of cache issues in a NoC-based shared-memory MP-SoCs and the student, after doing some bibliographies about NoC, caches, and shared memory MP-SoCs, will try to define and design the necessary cost-efficient features needed to be provided by the network routers and caches to keep the transparency of shared caches even if they are distributed over the network. And then he will develop a SystemC CABA (Cycle-Accurate Bit-Accurate) model of these components. The simulation platform baseline will be SoCLib developed in LIP6 laboratory in Paris. So we will be in close collaboration with researchers of LIP6 in particular Prof. Alain Greiner. And as the next step of this PhD research the student will try to define an optimization algorithm to find the best places for caches in different network topologies.